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| CS5374 Dual High-performance Amplifier & Modulator Features High Input Impedance Differential Amplifier * Ultra-low input bias: < 1 pA * Max signal amplitude: 5 Vpp differential Description The CS5374 combines two marine seismic analog measurement channels into one 7 mm x 7 mm QFN package. Each measurement channel consists of a high input impedance programmable gain differential amplifier that buffers analog signals into a high-performance, fourth-order modulator. The low-noise modulator converts the analog signal into a one-bit serial bit stream suitable for the CS5376A digital filter. Each amplifier has two sets of external inputs, INA and INB, to simplify system design as inputs from a hydrophone sensor or the CS4373A test DAC. An internal 800 termination can also be selected for noise tests. Gain settings are binary weighted (1x, 2x, 4x, 8x, 16x, 32x, 64x) and match the CS4373A test DAC output attenuation settings for full-scale testing at all gain ranges. Both the input multiplexer and gain are set by registers accessed through a standard SPITM port. Each fourth-order modulator has very high dynamic range combined with low total harmonic distortion and low power consumption. It converts differential analog signals from the amplifier to an oversampled serial bit stream which is decimated by the CS5376A digital filter to a 24-bit output at the final output word rate. ORDERING INFORMATION See page 43. OUT1+ OUT1INR1- INF1- INF1+INR1+ VA- VA+ Fourth Order Delta-Sigma () Modulator * Signal Bandwidth: DC to 2 kHz * Common mode rejection: 110 dB CMRR Differential Analog Input, Digital Output * Multiplexed inputs: INA, INB, 800 termination * Selectable Gain: 1x, 2x, 4x, 8x, 16x, 32x, 64x Excellent Amplifier Noise Performance * 1.5 Vpp between 0.1 Hz and 10 Hz * 11 nV / Hz from 200 Hz to 2 kHz High Modulator Dynamic Range * 126 dB SNR @ 215 Hz BW (2 ms sampling) * 123 dB SNR @ 430 Hz BW (1 ms sampling) Low Total Harmonic Distortion * -118 dB THD typical (0.000126%) * -108 dB THD maximum (0.0004%) Low Power Consumption * Normal operation: 6.5 mA per channel * Power down: 15 A per channel max Dual Power Supply Configuration * VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V GUARD1 INA1+ INB1+ 400 + GAIN1 Reset, Clock, and Synchronization RST MCLK MSYNC MUX1 400 INA1INB1VA+ VAINA2+ INB2+ 400 + 4th Order Modulator MDATA1 MFLAG1 CS5374 + GAIN2 VD GND 4th Order Modulator MDATA2 MFLAG2 MUX2 400 INA2INB2GUARD2 + OUT2+ OUT2INR2- INF2- INF2+INR2+ SPITM Serial Interface SDO SDI SCLK CS VREF+ VREF- Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved) OCT '09 DS862F1 CS5374 DS862F1 TABLE OF CONTENTS CS5374 1. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 4 SPECIFIED OPERATING CONDITIONS ................................................................................ 4 ABSOLUTE MAXIMUM RATINGS .......................................................................................... 4 THERMAL CHARACTERISTICS ............................................................................................. 5 ANALOG CHARACTERISTICS ............................................................................................... 5 PERFORMANCE SPECIFICATIONS ...................................................................................... 7 CHANNEL PERFORMANCE PLOTS ...................................................................................... 9 DIGITAL CHARACTERISTICS .............................................................................................. 10 SPITM INTERFACE TIMING (EXTERNAL MASTER) ............................................................ 12 POWER SUPPLY CHARACTERISTICS ............................................................................... 13 2. GENERAL DESCRIPTION..................................................................................................... 14 3. AMPLIFIER OPERATION ...................................................................................................... 16 3.1 Amplifier Inputs -- INA, INB .......................................................................................... 16 3.1.1 Multiplexer Settings -- MUX ............................................................................... 16 3.1.2 Gain Settings -- GAIN ........................................................................................ 16 3.2 Amplifier Outputs -- OUTR, OUTF ............................................................................... 16 3.2.1 Guard Output -- GUARD.................................................................................... 16 3.3 Differential Signals ........................................................................................................ 17 4. MODULATOR OPERATION .................................................................................................. 18 4.1 Modulator Anti-Alias Filter ............................................................................................. 18 4.2 Modulator Inputs -- INR, INF ........................................................................................ 19 4.2.1 Modulator Input Impedance ................................................................................ 19 4.2.2 Modulator Idle Tones -- OFST ........................................................................... 19 4.3 Modulator Output -- MDATA ........................................................................................ 19 4.3.1 Modulator One's Density ..................................................................................... 19 4.3.2 Decimated 24-bit Output ..................................................................................... 19 4.4 Modulator Stability -- MFLAG....................................................................................... 20 4.5 Modulator Clock Input -- MCLK.................................................................................... 20 4.6 Modulator Synchronization -- MSYNC ......................................................................... 20 5. SPITM SERIAL PORT ............................................................................................................. 21 5.1 SPI Pin Descriptions ..................................................................................................... 21 5.2 SPI Serial Transactions................................................................................................. 21 5.3 SPI Registers ................................................................................................................ 23 5.3.1 VERSION -- 0x00............................................................................................... 23 5.3.2 AMP1CFG -- 0x01 ............................................................................................. 23 5.3.3 AMP2CFG -- 0x02 ............................................................................................. 23 5.3.4 ADCCFG -- 0x03................................................................................................ 24 5.3.5 PWRCFG -- 0x04 ............................................................................................... 24 5.4 Example: CS5374 Configuration by an External SPI Master ........................................ 24 5.5 Example: CS5374 Configuration by the CS5376A SPI 2 Port ...................................... 25 5.5.1 CS5376A SPI 1 Transactions ............................................................................. 25 6. POWER MODES .................................................................................................................... 29 6.1 Normal Operation .......................................................................................................... 29 6.2 Power Down, MCLK Enabled........................................................................................ 29 6.3 Power Down, MCLK Disabled ....................................................................................... 29 7. VOLTAGE REFERENCE ....................................................................................................... 30 7.1 VREF Power Supply ..................................................................................................... 30 7.2 VREF RC Filter ............................................................................................................. 30 7.3 VREF PCB Routing ....................................................................................................... 30 7.4 VREF Input Impedance................................................................................................. 30 7.5 VREF Accuracy............................................................................................................. 31 8. POWER SUPPLIES .............................................................................................................. 32 8.1 Analog Power Supplies ................................................................................................. 32 8.2 Digital Power Supply ..................................................................................................... 32 8.3 Power Supply Bypassing .............................................................................................. 32 2 DS862F1 CS5374 DS862F1 CS5374 8.4 PCB Layers and Routing............................................................................................... 33 8.5 Power Supply Rejection ................................................................................................ 33 8.6 SCR Latch-up Considerations....................................................................................... 33 8.7 DC-DC Converters ........................................................................................................ 33 9. SPITM REGISTER SUMMARY................................................................................................ 34 9.1 VERSION: 0x00 ............................................................................................................ 35 9.2 AMP1CFG: 0x01 ........................................................................................................... 36 9.3 AMP2CFG: 0x02 ........................................................................................................... 37 9.4 ADCCFG: 0x03 ............................................................................................................. 38 9.5 PWRCFG: 0x04 ............................................................................................................ 38 10. PIN DESCRIPTIONS ............................................................................................................. 40 11. PACKAGE DIMENSIONS ...................................................................................................... 42 12. ORDERING INFORMATION ................................................................................................. 43 13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ........................... 43 14. REVISION HISTORY ............................................................................................................ 44 LIST OF FIGURES Figure 1. External Anti-alias Filter Components.............................................................................. 6 Figure 2. CS5374 Amplifier Noise Performance ............................................................................. 7 Figure 3. CS5374 Noise Performance (1x Gain) ........................................................................... 9 Figure 4. CS5374 + CS4373A Test DAC Dynamic Performance ................................................... 9 Figure 5. Digital Rise and Fall Times SYNC from external system............................................... 10 Figure 6. System Synchronization Diagram.................................................................................. 10 Figure 7. MCLK / MSYNC Timing Detail ....................................................................................... 11 Figure 8. SDI Write Timing in SPI Slave Mode ............................................................................. 12 Figure 9. SDO Read Timing in SPI Slave Mode ........................................................................... 12 Figure 10. CS5374 System Block Diagram................................................................................... 14 Figure 11. CS5374 Connection Diagram ...................................................................................... 15 Figure 12. CS5374 to CS5376A Digital Interface.......................................................................... 15 Figure 13. CS5374 Amplifier Block Diagram................................................................................. 16 Figure 14. CS5374 Modulator Block Diagram............................................................................... 18 Figure 15. SPI Interface Block Diagram........................................................................................ 21 Figure 16. CS5374 (Slave) Serial Transactions with CS5376A (Master)...................................... 22 Figure 17. Power Mode Diagram .................................................................................................. 29 Figure 18. Voltage Reference Circuit ............................................................................................ 30 Figure 19. Power Supply Diagram ................................................................................................ 32 Figure 20. Hardware Version ID Register VERSION .................................................................... 35 Figure 21. Amplifier 1 Configuration Register AMP1CFG............................................................. 36 Figure 22. Amplifier 2 Configuration Register AMP2CFG............................................................. 37 Figure 23. Modulator 1 & 2 Configuration Register ADCCFG....................................................... 38 Figure 24. Power Configuration Register PWRCFG ..................................................................... 39 LIST OF TABLES Table 1. 24-bit Output Coding ...................................................................................................... 20 Table 2. SPI Configuration Registers ........................................................................................... 23 Table 3. Digital Selections for Gain and Input Mux Control ......................................................... 23 Table 4. Example SPI Transactions to Write and Read the CS5374 Configuration Registers .... 24 Table 5. Example CS5376A SPI 1 Transactions to Write and Read the GPCFG0 Register ....... 25 Table 6. Example CS5376A SPI 1 Transactions to Write the CS5374 AMP1CFG Register ....... 26 Table 7. Example CS5376A SPI 1 Transactions to Write AMP2CFG and ADCCFG .................. 27 Table 8. Example CS5376A SPI 1 Transactions to Write the CS5374 PWRCFG Register ......... 28 DS862F1 3 CS5374 DS862F1 1. * * * * CS5374 CHARACTERISTICS AND SPECIFICATIONS Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C. GND = 0 V, all voltages with respect to 0 V. Device connected as shown in Figure 11 and Figure 12 unless otherwise noted. SPECIFIED OPERATING CONDITIONS Parameter Bipolar Power Supplies Positive Analog Negative Analog Positive Digital Voltage Reference [VREF+] - [VREF-] VREFThermal Ambient Operating Temperature Symbol +2% (Note 1) +2% +3% (Note 2, 3) (Note 4) -CNZ VA+ VAVD VREF VREFTA Min 2.45 -2.45 3.20 -10 Nom 2.50 -2.50 3.30 2.500 VA 25 Max 2.55 -2.55 3.40 70 Unit V V V V V C Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions. 2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance. 3. Channel-to-channel gain accuracy is directly proportional to the voltage reference absolute accuracy. 4. VREF inputs must satisfy: VA- VREF- < VREF+ VA+. ABSOLUTE MAXIMUM RATINGS Parameter Positive Analog Negative Analog Digital Analog Supply Differential [(VA+) - (VA-)] Digital Supply Differential [(VD) - (VA-)] Input Current, Any Pin Except Supplies (Note 5, 6) Input Current, Power Supplies (Note 5) Output Current (Note 5) Power Dissipation Analog Input Voltages Digital Input Voltages Storage Temperature Range DC Power Supplies Symbol VA+ VAVD VADIFF VDDIFF IIN IPWR IOUT PD VINA VIND TSTG Min -0.3 -6.8 -0.3 (VA-)-0.5 -0.5 -65 Max 6.8 0.3 6.8 6.8 6.8 +10 +50 +25 500 (VA+)+0.5 (VD)+0.5 150 Unit V V V V V mA mA mA mW V V C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 5. Transient currents up to 100mA will not cause SCR latch-up. 6. Includes continuous over-voltage conditions on the analog input pins. 4 DS862F1 CS5374 DS862F1 THERMAL CHARACTERISTICS Parameter Ambient Operating Temperature Storage Temperature Range Allowable Junction Temperature Junction to Ambient Thermal Impedance (4-layer PCB) Symbol TA TSTR TJCT JA Min -10 -65 Typ 26 Max 70 150 125 - CS5374 Unit C C C C / W ANALOG CHARACTERISTICS Parameter Amplifier Inputs Signal Frequencies Differential Gain Common Mode Gain Common Mode Voltage Voltage Range (Signal + Vcm) Full Scale Differential Input x1 x2 - x64 x1 x2 x4 x8 x16 x32 x64 (Note 7) BW GAIN GAINCM Vcm VIN DC x1 (VA-)+0.7 (VA-)+0.7 Symbol Min Typ x1 (VA-)+2.5 Max 2000 x64 (VA+)-1.25 (VA+)-1.75 Unit Hz V V Vpp Vpp Vpp mVpp mVpp mVpp mVpp T, pF T, pF pA Vpp V /C mA nF V A pF 1, 20 0.5, 40 1 40 0.38 Vcm 500 - VINFS (VA-)+0.5 5 2.5 1.25 625 312.5 156.25 78.125 40 5 (VA+)-0.5 Differential Input Impedance Common Mode Input Impedance Input Bias Current Amplifier Outputs Full Scale Output, Differential Output Voltage Range (Signal + Vcm) Output Impedance Output Impedance Drift Output Current Load Capacitance Guard Outputs Guard Output Voltage Guard Output Impedance Guard Output Current Guard Load Capacitance (Note 8) (Note 8) (Note 8) ZINDIFF ZINCM IIN VOUT VRNG ZOUT ZTC IOUT CL VGUARD ZGOUT IGOUT CGL - +25 100 40 100 Notes: 7. Common mode signals pass through the differential amplifier architecture and are rejected by the modulator CMRR. 8. Output impedance characteristics are approximate and can vary up to 30% depending on process parameters. DS862F1 5 CS5374 DS862F1 ANALOG CHARACTERISTICS (CONT.) Parameter Modulator Inputs Input Signal Frequencies Full-scale Differential AC Input Full-scale Differential DC Input Input Common Mode Voltage Input Voltage Range (Vcm Signal ) Differential Input Impedance Single-ended Input Impedance External Anti-alias Filter (Note 10) VREF Inputs [VREF+] - [VREF-] VREFVREF Input Current VREF Input Noise (Note 11) (Note 2, 3) (Note 4) VREF VREFVREFII VREFIN 2.500 VA 120 1 INR INF INR INF Series Resistance Differential Capacitance (Note 9) VBW VAC VDC VCM VRNG ZDIFINR ZDIFINF ZSEINR ZSEINF RAA CDIFF DC -2.5 (VA-)+0.7 CS5374 Min Typ (VA-)+2.5 Symbol Max 2000 5 2.5 (VA+)-1.25 Unit Hz Vpp VDC V V k M k M nF V V A Vrms 20 1 40 2 680 20 - - Notes: 9. The upper bandwidth limit is determined by the selected digital filter cut-off frequency. 10. Anti-alias capacitors are discrete external components and must be of good quality (C0G, NPO, poly). Poor-quality capacitors will degrade total harmonic distortion (THD) performance. See Figure 1 for external anti-alias filter connections. 11. Maximum integrated noise over the measurement bandwidth for the voltage reference device attached to the VREF inputs. CS5374 680 OUT+ INR+ INF+ 680 680 OUT680 20nF C0G 20nF C0G INFINR- AMPLIFIER MODULATOR Figure 1. External Anti-alias Filter Components 6 DS862F1 CS5374 DS862F1 PERFORMANCE SPECIFICATIONS Parameter Amplifier Noise Voltage Noise Voltage Noise Density Current Noise Density Channel Dynamic Range Dynamic Range (1x Gain, Multiple OWRs) (Note 9, 12) (1/4 ms) DC to 1720 Hz (1/2 ms) DC to 860 Hz (1 ms) DC to 430 Hz (2 ms) DC to 215 Hz (4 ms) DC to 108 Hz (8 ms) DC to 54 Hz (16 ms) DC to 27 Hz 1x 2x 3x 8x 16x 32x 64x 1x 2x 4x 8x 16x 32x 64x SNR 121 121 105 120 123 126 129 131 135 123 122 120 116 111 105 98 -118 -119 -119 -119 -118 -115 -112 -108 f0 = 0.1 Hz to 10 Hz f0 = 200 Hz to 2 kHz VNPP VND IND 1.5 11 20 3 14 Symbol Min Typ Max CS5374 Unit Vpp nV/ Hz fA/ Hz dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Dynamic Range (Multiple Gains, 1 ms OWR) (Note 9, 12) SNR Channel Distortion Total Harmonic Distortion (Note 13) THD Notes: 12. Dynamic Range defined as 20 log [(RMS full scale) / (RMS idle noise)] where idle noise is measured with the amplifier input terminated. Dynamic Range is dominated by high-frequency quantization noise at the 1/4 ms rate and amplifier noise at high gain. 13. Tested with a 31.25 Hz sine wave at 1 ms sampling rate and -1 dB amplitude. CS5374 Amplifier In-Band Noise 20 CS5374 Amplifier Wide Band Noise 400 Noise Density (nV/rtHz) 15 Noise Density (nV/rtHz) 300 10 200 5 100 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) 0 0.1 1 10 100 1k 10k 100k 1M Frequency (Hz) Figure 2. CS5374 Amplifier Noise Performance DS862F1 7 CS5374 DS862F1 PERFORMANCE SPECIFICATIONS (CONT.) CS5374 Parameter Channel Gain Accuracy Channel Gain, Offset Corrected Absolute Gain Accuracy Relative Gain Accuracy (Note 16) (Note 3, 14) (Note 3, 15) 2x 4x 8x 16x 32x 64x (Note 17) GAINLSB GAINABS -6101194 0xA2E736 6101194 0x5D18CA CS5374 Symbol Min Typ Max Unit LSB LSB % % % % % % % ppm / C V V / C mV mV mV V / C V %FS dB dB dB -0.3 - 1 -0.1 -0.1 0.1 0.4 0.4 0.3 25 250 0.3 1 -60 -35 1 1 100 110 -130 -130 +2 0.1 750 - GAINREL Gain Drift Channel Offset Accuracy Amplifier Offset Voltage, Input Referred Amplifier Offset Drift, Input Referred Modulator Offset Voltage, Differential Modulator Offset Voltage, Channel 1 Modulator Offset Voltage, Channel 2 Modulator Offset Drift Offset After Calibration Offset Calibration Range Channel CMRR and Crosstalk Common Mode Rejection Ratio Crosstalk, Amplifier Multiplexed Inputs Crosstalk, Channel-to-Channel GAINTC (Note 18) OFSTAMP (Note 17) OFSTATC (OFST = 1) OFSTMOD (OFST = 0) OFSTMOD1 (OFST = 0) OFSTMOD2 (Note 17) OFSTMTC (Note 19) OFSTCAL (Note 20) OFSTRNG CMRR CXTMI CXTCC Notes: 14. Channel Gain is the nominal full-scale 24-bit output code from the CS5376A digital filter for a 5 VPP differential signal into the CS5374 analog inputs at 1x gain. Value is offset corrected. 15. Absolute gain accuracy tests the matching of 1x gain across multiple CS5374 channels in a system. 16. Relative gain accuracy tests the tracking of 2x, 4x, 8x, 16x, 32x, 64x gain relative to 1x gain on a single CS5374 channel. 17. Specification is for the parameter over the specified temperature range and is for the CS5374 device only. It does not include the effects of external components. 18. Offset voltage is tested with the amplifier inputs connected to the internal 800 termination. 19. The offset after calibration specification is measured from the digitally calibrated output codes of the CS5376A digital filter. 20. Offset calibration is performed in the CS5376A digital filter and includes the full-scale signal range. 8 DS862F1 CS5374 DS862F1 CHANNEL PERFORMANCE PLOTS CS5374 Figure 3. CS5374 Noise Performance (1x Gain) Figure 4. CS5374 + CS4373A Test DAC Dynamic Performance DS862F1 9 CS5374 DS862F1 DIGITAL CHARACTERISTICS Parameter Digital Inputs High-level Input Voltage Low-level Input Voltage Input Leakage Current Digital Input Capacitance Input Rise Times Except MCLK Input Fall Times Except MCLK Digital Outputs High-level Output Voltage, Iout = -40 A Low-level Output Voltage, Iout = 40 A High-Z Leakage Current Digital Output Capacitance Output Rise Times Output Fall Times (Note 22) (Note 22) VOH VOL IOZ COUT tRISE tFALL VD - 0.3 1 9 0.3 10 100 100 (Note 21) (Note 21) VIH VIL IIN CIN tRISE tFALL 0.6*VD 0.0 1 9 VD 0.8 10 100 100 Symbol Min Typ Max CS5374 Unit V V A pF ns ns V V A pF ns ns Notes: 21. Device is intended to be driven with CMOS logic levels. 22. Guaranteed by design and/or characterization. t rise t fa ll 0.9 * VD 0.1 * V D Figure 5. Digital Rise and Fall Times SYNC from external system. SYNC MCLK MSYNC t0 MDATA MFLAG TDATA Figure 6. System Synchronization Diagram SYNC from External. MCLK, MSYNC, TDATA from CS5376A. MDATA, MFLAG from CS5374. 10 DS862F1 CS5374 DS862F1 DIGITAL CHARACTERISTICS (CONT.) Parameter Master Clock Input MCLK Frequency MCLK Duty Cycle MCLK Rise Time MCLK Fall Time MCLK Jitter (in-band or aliased in-band) MCLK Jitter (out-of-band) Master Sync Input MSYNC Setup Time to MCLK Falling MSYNC Period MSYNC Hold Time after MCLK Falling MDATA Output MDATA Output Bit Rate MDATA Output One's Density Range Full-scale Output Code, Offset Corrected (Note 22) (Note 25) fMDATA MDAT1D MDATFS 14 0xA2E736 CS5374 Min 40 20 40 20 Typ 2.048 366 976 610 512 - Symbol (Note 23) fMCLK MCLKDTC tRISE tFALL MCLKIBJ MCLKOBJ (Note 24) (Note 24) (Note 24) tMSS tMSYNC tMSH Max 60 50 50 300 1 86 0x5D18CA Unit MHz % ns ns ps ns ns ns ns kbits/s % Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the CS5374 device automatically enters a power-down state. See Power Supply Characteristics for typical power-down timing. 24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge, synchronization instant (t0) is on the next MCLK rising edge. 25. Decimated, filtered, and offset-corrected 24-bit output word from the CS5376A digital filter. MCLK tMSS tMSH 1 / fMCLK MSYNC t0 tMSYNC MDATA 1 / fMDATA MFLAG Figure 7. MCLK / MSYNC Timing Detail DS862F1 11 CS5374 DS862F1 SPITM INTERFACE TIMING (EXTERNAL MASTER) Parameter SDI Write Timing CS Enable to Valid Latch Clock Data Set-up Time Prior to SCK Rising Data Hold Time After SCK Rising SCK High Time SCK Low Time SCK Falling Prior to CS Disable SDO Read Timing SCK Falling to New Data Bit SCK High Time SCK Low Time SCK Falling Hold Time Prior to CS Disable t7 t8 t9 t10 120 120 60 90 t1 t2 t3 t4 t5 t6 60 60 60 120 120 60 Symbol Min Typ Max CS5374 Unit ns ns ns ns ns ns ns ns ns ns CS SDI MSB t1 MSB - 1 t2 t3 t4 t5 LSB t6 SCK Figure 8. SDI Write Timing in SPI Slave Mode CS SDO MSB t7 MSB - 1 t8 t9 LSB t10 SCK Figure 9. SDO Read Timing in SPI Slave Mode 12 DS862F1 CS5374 DS862F1 POWER SUPPLY CHARACTERISTICS Parameter Power Supply Current, ch1 + ch2 combined Analog Power Supply Current Digital Power Supply Current Power Supply Current, ch1 or ch2 only Analog Power Supply Current Digital Power Supply Current Power Down Current, MCLK enabled Analog Power Supply Current Digital Power Supply Current Power Down Current, MCLK disabled Analog Power Supply Current Digital Power Supply Current Power Down Timing (after MCLK disabled) Power Supply Rejection Power Supply Rejection Ratio (Note 22) PSRR 100 (Note 26) (Note 26) (Note 22) IA ID PDTC 2 1 40 15 15 (Note 26) (Note 26) IA ID 150 10 250 75 (Note 26) (Note 26) IA ID 6.5 25 8 50 (Note 26) (Note 26) IA ID 13 50 16 100 Symbol Min Typ Max CS5374 Unit mA A mA A A A A A S dB Notes: 26. All outputs unloaded. Digital inputs forced to VD or GND respectively. Amplifier inputs connected to the 800 internal termination. DS862F1 13 CS5374 DS862F1 CS5374 Hydrophone Sensor M U X CS5374 AMP DS Modulator Hydrophone Sensor M U X AMP DS Modulator CS5376A Microcontroller or Configuration EEPROM Digital Filter CS5374 Hydrophone Sensor M U X AMP DS Modulator System Telemetry Hydrophone Sensor M U X CS4373A AMP DS Modulator Test DAC Figure 10. CS5374 System Block Diagram 2. GENERAL DESCRIPTION er and gain are set by registers accessed through a standard SPITM port. Each fourth-order modulator has very high dynamic range combined with low total harmonic distortion and low power consumption. It converts differential analog signals from the amplifier to an oversampled serial bit stream which is decimated by the CS5376A digital filter to a 24-bit output at the final output word rate. Figure 10 shows the system-level architecture of a 4-channel acquisition system using two CS5374, one CS5376A digital filter and one CS4373A test DAC. Figure 11 and Figure 12 shows connection diagrams for the CS5374 device when connected to the CS5376A digital filter. The CS5374 combines two marine seismic analog measurement channels into one 7 mm x 7 mm QFN package. Each measurement channel consists of a high input impedance programmable gain differential amplifier that buffers analog signals into a high-performance, fourth-order modulator. The low-noise modulator converts the analog signal into a one-bit serial bit stream suitable for the CS5376A digital filter. Each amplifier has two sets of external inputs, INA and INB, to simplify system design as inputs from a hydrophone sensor or the CS4373A test DAC. An internal 800 termination can also be selected for noise tests. Gain settings are binary weighted (1x, 2x, 4x, 8x, 16x, 32x, 64x) and match the CS4373A test DAC output attenuation settings for full-scale testing at all gain ranges. Both the input multiplex- 14 DS862F1 CS5374 DS862F1 680 680 680 CS5374 VA- 0.02 F C0G 0.02 F C0G VA+ 0.1F 0.1 F 680 GUARD1 INA1+ Hydrophone Sensor INA1OUT1+ INR1OUT1- INF1INF1+ INR1+ VA- VA+ RST Reset, Clock, and Synchronization MCLK MSYNC 400 + GAIN1 A MUX1 400 INB1+ CS4373A Test DAC INB1VA+ 0.1 F + 4th Order Modulator MDATA1 MFLAG 1 VA0.1 F VA+ VAINB2+ 400 INB2- CS5374 + GAIN2 VD+ GND 0.01F To CS5376A Digital Control 4th Order Modulator MDATA2 MFLAG 2 MUX2 400 SDO SPITM Serial Communications Interface SDI SCLK CS INF2+ INF2INR2+ VREF+ VREF- INA2+ Hydrophone Sensor INA2- + GUARD2 OUT2+ OUT2INR2- 680 680 680 0.02 F C0G 0.02 F C0G 2.5V Precision Voltage Reference 680 Figure 11. CS5374 Connection Diagram EXTERNAL RESET CONTROLLER RST Reset, Clock, and Synchronization MCLK MSYNC RESET MCLK MSYNC Clock and Synchronization 4 Order Modulator th MDATA1 MFLAG1 MDATA1 MFLAG1 CS5374 4 Order Modulator th Modulator Data Interface CS5376A MDATA2 MFLAG2 MDATA2 MFLAG2 SDO SPITM Serial Communications Interface SDI SCLK CS SI1 SO SCK2 CS0 SPI 2 Serial Peripheral Interface 2 Figure 12. CS5374 to CS5376A Digital Interface DS862F1 15 CS5374 DS862F1 GUARD1 INA1+ INB1+ 400 OUT1+ OUT1- CS5374 + GAIN1 MUX1 400 INA1INB1- + Figure 13. CS5374 Amplifier Block Diagram 3. AMPLIFIER OPERATION mode. The CS5374 mux switches will maintain good linearity only with minimal signal current. 3.1.2 Gain Settings -- GAIN The CS5374 high-impedance, low-noise CMOS differential input, differential output amplifiers are optimized for precision analog signals between DC and 2 kHz. They have multiplexed inputs and programmable gains of 1x, 2x, 4x, 8x, 16x, 32x, and 64x. The performance of this amplifier makes it ideal for low-frequency, high-dynamic-range applications requiring low distortion and minimal power consumption. The CS5374 supports gain ranges of 1x, 2x, 4,x 8x, 16x, 32x, and 64x. Amplifier gain is selected using internal configuration registers accessed through the SPI port, see the "SPITM Register Summary" on page 34 for more information. 3.1 Amplifier Inputs -- INA, INB The amplifier analog inputs are designed for highimpedance differential hydrophone sensors and so have very low input bias below 1 pA. 3.1.1 Multiplexer Settings -- MUX 3.2 Amplifier Outputs -- OUTR, OUTF The amplifier analog outputs are externally separated into rough / fine charge signals to connect into the modulator inputs. Each differential output requires two series resistors and a differential capacitor to create the modulator anti-alias RC filter. 3.2.1 Guard Output -- GUARD Input multiplexing simplifies system connections by providing separate inputs for a sensor and test DAC (INA, INB) as well as an internal termination for noise tests. The multiplexer determines which input is connected to the amplifier, and is set through internal configuration registers accessed through the SPI port, see the "SPITM Register Summary" on page 34 for more information. Although a mux selection is provided to enable the INA and INB switches simultaneously, significant current should not be driven through them in this 16 The GUARD pin outputs the common mode voltage of the selected analog signal input. It can be used to drive the cable shield between a high-impedance sensor and the amplifier inputs. Driving the cable shield with the analog signal common mode voltage minimizes leakage and improves signal integrity from high-impedance sensors. The GUARD output is defined as the midpoint voltage between the + and - halves of the currently DS862F1 CS5374 DS862F1 selected differential input signal, and will vary as the signal common mode varies. The GUARD output will not drive a significant load, as it can only provide a shielding voltage. CS5374 3.3 Differential Signals Analog signals into and out of the amplifiers are differential, consisting of two halves with equal but opposite magnitude varying about a common mode voltage. A full-scale 5 Vpp differential signal centered on a -0.15 V common mode can have: SIG+ = -0.15 V + 1.25 V = 1.1 V SIG- = -0.15 V - 1.25 V = -1.4 V SIG+ is +2.5 V relative to SIGFor the reverse case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = 1.1 V SIG+ is -2.5 V relative to SIGThe total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp. A similar calculation can be done for SIG- relative to SIG+. Note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds 1.1 V and never drops below -1.4 V on either half of the signal. By definition, differential voltages are to be measured with respect to the opposite half, not relative to ground. A multi-meter differentially measuring between SIG+ and SIG- in the above example would properly read 1.767 Vrms, or 5 Vpp. DS862F1 17 CS5374 DS862F1 INR1- INF1- INF1+INR1+ VREF+ VREF- CS5374 Reset, Clock, and Synchronization RST MCLK MSYNC 4th Order Modulator MDATA1 MFLAG1 Figure 14. CS5374 Modulator Block Diagram 4. MODULATOR OPERATION vent high-frequency signals from aliasing into the measurement bandwidth. The use of simple, single-pole, differential, low-pass RC filters across the INR and INF inputs ensures high-frequency signals are rejected before they can alias into the measurement bandwidth. The approximate -3 dB corner of the input antialias filter is nominally set to the internal analog sampling rate divided by 64, which itself is a division by 4 of the MCLK rate. * * * * MCLK Frequency = 2.048 MHz Sampling Frequency = MCLK / 4 = 512 kHz -3 dB Filter Corner = Sampling Freq / 64 = 8 kHz RC filter = 1 / [ 2 x (2 x Rseries) x Cdiff ] ~ 8 kHz The CS5374 modulators are fourth-order type optimized for extremely high-resolution measurement of signals between DC and 2000 Hz. When combined with the internal differential amplifiers, the CS4373A test DAC and CS5376A digital filter, a small, low-power, self-testing, high-accuracy, multi-channel measurement system results. The modulators have high dynamic range and low total harmonic distortion with very low power consumption. They are optimized for extremely highresolution measurement of 5 Vp-p or smaller differential signals. They convert analog input signals from the differential amplifiers to an oversampled serial bit stream which is then passed to the digital filter. The companion CS5376A digital filter generates the clock and synchronization inputs for the modulators while receiving the one-bit data and overrange flag outputs. The digital filter decimates the modulator's oversampled output bit stream to a high-resolution, 24-bit output at the final selected output word rate. 4.1 Modulator Anti-Alias Filter The modulator inputs are required to be bandwidth limited to ensure modulator loop stability and pre18 Figure 1 on page 6 illustrates the CS5374 amplifier-to-modulator analog connections with input anti-alias filter components. Filter components on the rough and fine pins should be identical values for optimum performance, with the capacitor values a minimum of 0.02 F. The rough input can use either X7R or C0G-type capacitors, while the fine input requires C0G-type capacitors for optimal linearity. Using X7R-type capacitors on the fine analog inputs will significantly degrade total harmonic distortion performance. DS862F1 CS5374 DS862F1 4.2 Modulator Inputs -- INR, INF The modulator analog inputs are separated into differential rough and fine signals (INR, INF) to maximize sampling accuracy. The positive half of the differential input signal is connected to INR+ and INF+, while the negative half is attached to INF- and INR-. The INR pins are switched-capacitor `rough charge' inputs that pre-charge the internal analog sampling capacitor before it is connected to the INF fine input pins. 4.2.1 Modulator Input Impedance CS5374 (channel 2) of internal differential offset during conversion to push idle tones out of the measurement bandwidth. Care should be taken to ensure external offset voltages do not negate the internally added differential offset, or idle tones will reappear. 4.3 Modulator Output -- MDATA The CS5374 modulators are designed to operate with the CS5376A digital filter. The digital filter generates the modulator clock and synchronization signals (MCLK and MSYNC) while receiving back the modulator one-bit conversion data and over-range flag (MDATA and MFLAG). 4.3.1 Modulator One's Density The modulator inputs have a dynamic switched-capacitor architecture and so have a rough charge input impedance that is inversely proportional to the input master clock frequency and the input capacitor size, [1 / (f * C)]. * * * MCLK = 2.048 MHz INR Internal Input Capacitor = 20 pF Impedance = [1 / (2.048 MHz * 20 pF)] = 24 k During normal operation the CS5374 modulators output a serial bit stream to the MDATA pin, with a one's density proportional to the differential amplitude of the analog input signal. The output bit rate from the MDATA output is a divide-by-four of the input MCLK, and so is nominally 512 kHz. The MDATA output has a 50% one's density for a mid-scale analog input, approximately 86% one's density for a positive full-scale analog input, and approximately 14% one's density for a negative full-scale analog input. One's density of the MDATA output is defined as the ratio of `1' bits to total bits in the serial bit stream output; i.e. an 86% one's density has, on average, a `1' value in 86 of every 100 output data bits. 4.3.2 Decimated 24-bit Output Internal to the modulator, the rough inputs (INR) pre-charge the sampling capacitor used by the fine inputs (INF), therefore the input current to the fine inputs is typically very low and the effective input impedance is an order of magnitude above the impedance of the rough inputs. 4.2.2 Modulator Idle Tones -- OFST The modulators are delta-sigma-type and so can produce "idle tones" in the measurement bandwidth when the differential input signal is a steadystate DC signal near mid-scale. Idle tones result from low-frequency patterns in the output data stream and appear in the measurement spectrum as small tones about -135 dB down from full scale. By default the OFST bit in the ADCCFG register is low and idle tones are eliminated within the modulator by adding -60 mV (channel 1) and -35 mV When the CS5374 modulators operate with the CS5376A digital filter, the final decimated, 24-bit, full-scale output code range depends if digital offset correction is enabled. With digital offset correction enabled within the digital filter, amplifier DS862F1 19 CS5374 DS862F1 offset and the modulator internal offset are removed from the final conversion result. CS5376A Digital Filter 24-Bit Output Code Offset Corrected 5D18CA 000000 A2E736 CH1 -60 mV Offset 5ADCCE FDC404 A0AB3A CH2 -35 mV Offset 5BCB22 FEB258 A1998E CS5374 4.5 Modulator Clock Input -- MCLK The CS5376A digital filter generates the master clock for the CS5374, typically 2.048 MHz, from a synchronous clock input from the external system. If MCLK is disabled during operation, the CS5374 will enter a power down state after approximately 40 S. By default, MCLK is disabled at reset and is enabled by writing the digital filter CONFIG register. MCLK must have low jitter to guarantee full analog performance, requiring a crystal- or VCXObased system clock input to the digital filter. Clock jitter on the digital filter CLK input directly translates to jitter on MCLK. Modulator Differential Analog Input Signal > + (VREF+5%) + VREF 0V - VREF > - (VREF+5%) Error Flag Possible Error Flag Possible Table 1. 24-bit Output Coding for the CS5374 Modulator and CS5376A Digital Filter Combination 4.6 Modulator Synchronization -- MSYNC The CS5374 modulators are designed to operate synchronously with other modulators in a distributed measurement network, so a rising edge on the MSYNC input resets the internal conversion state machine to synchronize analog sample timing. MSYNC is automatically generated by the CS5376A digital filter after receiving a synchronization signal from the external system, and is chipto-chip accurate within 1 MCLK period. The input SYNC signal to the CS5376A digital filter sets a common reference time t0 for measurement events, thereby synchronizing analog sampling across a measurement network. By default, MSYNC generation is disabled at reset and is enabled by writing the digital filter CONFIG register. The CS5374 MSYNC input is rising-edge triggered and resets the internal MCLK counter/divider to guarantee synchronous operation with other system devices. While the MSYNC signal synchronizes the internal operation of the modulators, by default, it does not synchronize the phase of the sine wave from the CS4373A test DAC unless enabled in the digital filter TBSCFG register. 4.4 Modulator Stability -- MFLAG The CS5374 modulators have a fourth-order architecture which is conditionally stable and may go into an oscillatory condition if the analog inputs are over-ranged more than 5% past either positive or negative full scale. If an unstable condition is detected, the modulator collapses to a first-order system to regain stability and transitions the MFLAG output low-to-high to signal an error condition to the CS5376A digital filter. The MFLAG output connects to a dedicated input on the digital filter, causing an error flag to be set in the status byte of the next output data word. The analog input signal must be reduced to within the full-scale range for at least 32 MCLK cycles for the modulator to recover from an oscillatory condition. If the analog input remains over-ranged for an extended period, the modulator will cycle between fourth-order and first- order operation and the MFLAG output will be seen to pulse. 20 DS862F1 CS5374 DS862F1 CS5374 RST CS SCLK SDI SDO Hardware Configuration SPI Registers Serial Pin Logic Figure 15. SPI Interface Block Diagram 5. SPITM SERIAL PORT 5.2 SPI Serial Transactions Following reset, master mode serial transactions to CS5374 assert CS and write serial clocks to SCLK while writing serial data into SDI or reading serial data out from SDO. The CS5374 serial port operates in SPI mode 0 (0,0) and reads or writes configuration registers using standard 8-bit SPI opcodes. Each individual serial transaction is 24-bits long and is generated by concatenating an 8-bit SPI command opcode, an 8bit register address, and an 8-bit data byte as shown in Figure 16 on page 22. The CS5374 SPI state machine requires 24 clocks with CS asserted to fully shift out the SPI data or else SPI clock synchronization can be lost. The CS5376A SPI 2 hardware generates 24 clocks per transaction and will keep the CS5374 serial port synchronized at all times. However, if another SPI master is used and clock synchronization is lost, two methods are available to recover: 1. Hold CS high (inactive) and apply 24 clocks to shift out any cached SPI data bits. This method retains the existing CS5374 register configuration. ... or ... 2. Apply a hardware reset (toggle RST) and then rewrite all CS5374 register configuration values. The CS5374 SPI interface is a slave serial port designed to interface with the CS5376A SPI 2 port. SPI commands from the CS5376A write and read the CS5374 configuration registers to control hardware operation. A block diagram of the CS5374 SPI serial interface is shown in Figure 15, and connections to the CS5376A SPI 2 port are shown in Figure 12 on page 15. 5.1 SPI Pin Descriptions RST -- Pin 37 Hardware reset input pin, active low. Defaults the configuration registers and SPI state machine. CS -- Pin 25 Chip select input pin, active low. SCLK -- Pin 26 Serial clock input pin. Maximum 4.096 MHz. SDI -- Pin 27 Serial data input pin. Data expected valid on rising edge of SCLK, transition on falling edge. SDO -- Pin 28 Serial data output pin. Data valid on rising edge of SCLK, transition on falling edge. DS862F1 21 CS5374 DS862F1 CS5374 Instruction Write Read Opcode 0x02 0x03 Address ADDR[7:0] ADDR[7:0] Definition Write SPI register specified by the address in ADDR. Read SPI register specified by the address in ADDR. CS5374 SPI Write from CS5376A SPI2 CS SDI 0x02 SPI2CMD[15:8] ADDR SPI2CMD[7:0] DATA SPI2DAT[23:16] SDO CS5374 SPI Read from CS5376A SPI2 CS SDI 0x03 SPI2CMD[15:8] ADDR SPI2CMD[7:0] SDO DATA SPI2DAT[23:16] SPI Mode 0 Transaction Details Cycle 1 2 3 4 5 6 7 8 SCLK SDI MSB 6 5 4 3 2 1 LSB SDO MSB 6 5 4 3 2 1 LSB X CS Figure 16. CS5374 (Slave) Serial Transactions with CS5376A (Master) 22 DS862F1 CS5374 DS862F1 Name VERSION AMP1CFG AMP2CFG ADCCFG PWRCFG CS5374 Description Addr. 0x00 0x01 0x02 0x03 0x04 Type R R/W R/W R/W R/W # Bits 8 8 8 8 8 Device Version ID Amplifier 1 configuration Amplifier 2 configuration Modulator 1 & 2 configuration Power configuration Table 2. SPI Configuration Registers 5.3 SPI Registers The CS5374 SPI registers are 8-bit registers that control the CS5374 hardware configuration. See "SPITM Register Summary" on page 34 for detailed bit definitions of the SPI registers listed in Table 2. 5.3.1 VERSION -- 0x00 5.3.2 AMP1CFG -- 0x01 The AMP1CFG register controls the amplifier MUX and GAIN settings for channel 1. It also enables PWDN mode for the channel 1 amplifier plus enables the GUARD output for channels 1 & 2. Reset Condition : 0000_0000 Normal Operation : 00MM_0GGG Power Down Operation : 1000_0000 The VERSION register indicates the hardware revision of the CS5374 device. Read only. Reset Condition : 0000_0001 Normal Operation : 0000_0001 Power Down Operation : 0000_0001 5.3.3 AMP2CFG -- 0x02 The AMP2CFG register controls the amplifier MUX and GAIN settings for channel 2. It also enables PWDN mode for the channel 2 amplifier. Reset Condition : 0000_0000 Normal Operation : 00MM_0GGG Power Down Operation : 1000_0000 Input Selection 800 termination INA only INB only INA + INB MUX1 0 1 0 1 MUX0 0 0 1 1 Gain Selection 1x 2x 4x 8x 16x 32x 64x reserved GAIN2 0 0 0 0 1 1 1 1 GAIN1 0 0 1 1 0 0 1 1 GAIN0 0 1 0 1 0 1 0 1 Table 3. Digital Selections for Gain and Input Mux Control DS862F1 23 CS5374 DS862F1 5.3.4 ADCCFG -- 0x03 5.3.5 PWRCFG -- 0x04 CS5374 The ADCCFG register can disable modulator OFST and enable HP mode. It also enables PWDN mode for the channel 1 & 2 modulators. Reset Condition : 0000_0000 Normal Operation : 0100_0000 Power Down Operation : 0011_0000 The PWRCFG register can vary bias currents for the amplifier and modulator to minimize power consumption. Reset Condition : 0000_0000 Normal Operation : 1000_1111 Power Down Operation : 0000_0000 5.4 Example: CS5374 Configuration by an External SPI Master Any SPI master that supports mode 0 (0,0) communication can write and read the configuration registers and control CS5374. The following example SPI read and write transactions show how to configure the CS5374 for normal operation. SPI Write Transactions Transaction 01 02 03 04 CS5374 SPI Write SI: 02 | 01 | 20 SO: ----------------SI: 02 | 02 | 20 SO: ----------------SI: 02 | 03 | 40 SO: ----------------SI: 02 | 04 | 8F SO: ----------------Description Write AMP1CFG register (0x01). CH1 INA enabled, 1x gain (0x20). Write AMP2CFG register (0x02). CH2 INA enabled, 1x gain (0x20). Write ADCCFG register (0x03). Normal operation (0x40). Write PWRCFG register (0x04). Normal operation (0x8F). SPI Read Transactions Transaction 01 02 03 04 05 CS5374 SPI Read SI: 03 | 00 | 00 SO: ---------- | 01 SI: 03 | 01 | 00 SO: ---------- | 20 SI: 03 | 02 | 00 SO: ---------- | 20 SI: 03 | 03 | 00 SO: ---------- | 40 SI: 03 | 04 | 00 SO: ---------- | 8F Description Read VERSION register (0x00). Returned data byte on the SO pin. Read AMP1CFG register (0x01). Returned data byte on the SO pin. Read AMP2CFG register (0x02). Returned data byte on the SO pin. Read ADCCFG register (0x03). Returned data byte on the SO pin. Read PWRCFG register (0x04). Returned data byte on the SO pin. Table 4. Example SPI Transactions to Write and Read the CS5374 Configuration Registers 24 DS862F1 CS5374 DS862F1 5.5 Example: CS5374 Configuration by the CS5376A SPI 2 Port The CS5374 SPI port was designed to connect to the CS5376A secondary SPI 2 port as shown in Figure 12 on page 15. The CS5376A SPI 2 hardware is controlled by writing internal digital filter registers SPI2CTRL, SPI2CMD, and SPI2DAT through a primary SPI 1 port. Chip selects are enabled by writing the GPCFG0 digital filter register prior to initiating SPI 2 transactions. Configuring CS5374 using SPI 2 is more complex than using an external SPI master, but has the advantage of a single standardized hardware interface (the primary SPI 1 port on CS5376A) to control the entire chipset. 5.5.1 CS5376A SPI 1 Transactions CS5374 contain internal commands to write the CS5376A digital filter registers that control the SPI 2 hardware and enable the chip selects. A full description of how to write the CS5376A internal digital filter registers using the primary SPI 1 port is described in the CS5376A data sheet. GPIO Register Certain GPIO pins on the CS5376A have dual-use as chip selects for the SPI 2 port. The GPIO0:CS0 and GPIO1:CS1 pins are recommended as dedicated chip selects when connecting two CS5374 devices to the CS5376A SPI 2 port. To operate the CS0 and CS1 pins as SPI 2 chip selects they must be programmed as outputs in the GPCFG0 digital filter register, as shown in Table 5. SPI2 Registers The CS5376A primary SPI 1 port is controlled by an external SPI master writing commands and data into the SPI 1 registers (SPICMD, SPIDAT1, and SPIDAT2). Serial transactions into the CS5376A primary SPI 1 port start with an SPI opcode, followed by an SPI address, and then data bytes written starting at that SPI address. These data bytes Three digital filter registers control the CS5376A SPI 2 hardware. The SPI2CMD register is 16-bits wide and contains the first two bytes of the SPI 2 transaction, the SPI opcode and SPI address, in the lower two bytes (i.e. 0x000204). Transaction 01 CS5376A Primary SPI 1 Write MOSI: 02 | 03 | 00 00 01 | 00 00 0E | 03 FF FF MISO: ----------------------------------------------------------- Description SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001 : Write Register SPIDAT1 : 0x00000E : GPCFG0 SPIDAT2 : 0x03FFFF : CS as Output See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000002: Read Register SPIDAT1 : 0x00000E : GPCFG0 SPIDAT2 : 0x000000 : Dummy See the CS5376A data sheet. SPI Command : 0x03 : Read SPI Address : 0x06 : SPIDAT1 SPIDAT1 : 0x03FFFF : GPCFG0 02 03 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 02 | 00 00 0E | 00 00 00 MISO: ----------------------------------------------------------- 04 05 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 03 | 06 |---------------| MISO: -------------| 03 FF FF | Table 5. Example CS5376A SPI 1 Transactions to Write and Read the GPCFG0 Register DS862F1 25 CS5374 DS862F1 The SPI2DAT register is 24-bits wide and can contain up to three bytes of data to follow the SPI opcode and address. For configuring the CS5374, however, only one data byte per register address is required and is written aligned with the upper byte (i.e. 0x8F0000). The SPI2CTRL register is 24-bits wide and configures/controls the SPI 2 hardware, with bit assignments detailed in the CS5376A data sheet. If the CS5374 GPIO:CS0 and GPIO1:CS1 pins are used as chip selects, separate SPI2CTRL values can initiate serial transactions to each device (i.e. 0x3F0161, 0x3F4162). Tables 6, 7, and 8 show the CS5376A primary SPI 1 transactions required to write the SPI 2 digital filter registers and configure two CS5374 devices for normal operation using the CS0 and CS1 chip selects. Transaction 01 CS5376A Primary SPI 1 Write MOSI: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 01 MISO: ----------------------------------------------------------- Description SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001 : Write Register SPIDAT1 : 0x000011 : SPI2CMD SPIDAT2 : 0x000201 : Write AMP1CFG See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000012 : SPI2DAT SPIDAT2 : 0x200000 : INA, x1 Gain See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F0161 : CS0 Transaction See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F4162 : CS1 Transaction 02 03 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 12 | 20 00 00 MISO: ----------------------------------------------------------- 04 05 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 01 61 MISO: ----------------------------------------------------------- 06 07 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 41 62 MISO: ----------------------------------------------------------- Table 6. Example CS5376A SPI 1 Transactions to Write the CS5374 AMP1CFG Register 26 DS862F1 CS5374 DS862F1 Transaction 01 CS5376A Primary SPI 1 Write MOSI: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 02 MISO: ----------------------------------------------------------Description CS5374 SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001 : Write Register SPIDAT1 : 0x000011 : SPI2CMD SPIDAT2 : 0x000202 : Write AMP2CFG See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000012 : SPI2DAT SPIDAT2 : 0x200000 : INA, x1 Gain See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F0161 : CS0 Transaction See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F4162 : CS1 Transaction 02 03 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 12 | 20 00 00 MISO: ----------------------------------------------------------- 04 05 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 01 61 MISO: ----------------------------------------------------------- 06 07 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 41 62 MISO: ----------------------------------------------------------- Transaction 01 CS5376A Primary SPI 1 Write MOSI: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 03 MISO: ----------------------------------------------------------- Description SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001 : Write Register SPIDAT1 : 0x000011 : SPI2CMD SPIDAT2 : 0x000203 : Write ADCCFG See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000012 : SPI2DAT SPIDAT2 : 0x400000 : Normal Operation See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F0161 : CS0 Transaction See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F4162 : CS1 Transaction 02 03 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 12 | 40 00 00 MISO: ----------------------------------------------------------- 04 05 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 01 61 MISO: ----------------------------------------------------------- 06 07 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 41 62 MISO: ----------------------------------------------------------- Table 7. Example CS5376A SPI 1 Transactions to Write AMP2CFG and ADCCFG DS862F1 27 CS5374 DS862F1 Transaction 01 CS5376A Primary SPI 1 Write MOSI: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 04 MISO: ----------------------------------------------------------Description CS5374 SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001 : Write Register SPIDAT1 : 0x000011 : SPI2CMD SPIDAT2 : 0x000204 : Write PWRCFG See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000012 : SPI2DAT SPIDAT2 : 0x8F0000 : Normal Operation See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F0161 : CS0 Transaction See the CS5376A data sheet. SPI Command : 0x02 : Write SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F4162 : CS1 Transaction 02 03 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 12 | 8F 00 00 MISO: ----------------------------------------------------------- 04 05 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 01 61 MISO: ----------------------------------------------------------- 06 07 Delay 1ms, monitor SINT, or poll E2DREQ MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 41 62 MISO: ----------------------------------------------------------- Table 8. Example CS5376A SPI 1 Transactions to Write the CS5374 PWRCFG Register 28 DS862F1 CS5374 DS862F1 CS5374 POWER DOWN MODE MCLK = OFF PWDN registers = X NORMAL OPERATION MCLK = ON PWDN registers = disabled POWER DOWN MODE MCLK = ON PWDN registers = enabled Figure 17. Power Mode Diagram 6. POWER MODES and all outputs are high impedance. In this mode power consumption is reduced, but not reduced as low as with MCLK inactive, as sections of the digital state machine are kept awake to support SPI communications. Any unused amplifier/modulator channels can be turned off individually through the configuration registers. The CS5374 amplifiers and modulators have three power modes. Normal operation, power down with MCLK enabled, and power down with MCLK disabled. Power down mode is controlled by PWDN bits in the SPI registers, and are active high. When PWDN is enabled, internal circuitry is disabled, the analog inputs and outputs go high-impedance, and the device enters a micro-power state. 6.3 Power Down, MCLK Disabled If MCLK is stopped, an internal loss-of-clock detection circuit automatically places the CS5374 into a power-down state. This power-down state is independent of the amplifier and modulator internal configuration registers, and is automatically invoked after approximately 40 s without receiving an incoming MCLK edge. During this power-down state, the amplifiers and modulators are disabled and all outputs are high impedance. The entire digital state machine goes inactive but configuration register values are retained, with a reset required to clear them. When used with the CS5376A digital filter, the CS5374 is in this lowest power-down state immediately after reset since MCLK is disabled by default. 6.1 Normal Operation With MCLK active and the amplifiers and modulators enabled (PWDN = 0) the CS5374 performs normal data acquisition. A differential analog input signal is converted to an oversampled 1-bit bit stream at 512 kHz. This bit stream is then digitally filtered and decimated by the CS5376A device to a high-precision 24-bit output. 6.2 Power Down, MCLK Enabled With MCLK active and all amplifiers and modulators disabled (PWDN = 1) the CS5374 is placed into a power-down state. During this power-down state the amplifiers and modulators are disabled DS862F1 29 CS5374 DS862F1 From VA+ Regulator CS5374 Route VREF as a differential pair from the 100uF RC filter capacitor 100 F 0.1 F 10 2.500 V VREF 0.1 F + 100 F 0.1 F To VREF+ From VARegulator 100 F 0.1 F 0.1 F To VREF- Figure 18. Voltage Reference Circuit 7. VOLTAGE REFERENCE A separate RC filter is required for each device connected to the voltage reference output. Signaldependent sampling of the voltage reference by one system device could cause unwanted tones to appear in the measurement bandwidth of another system device if a single VREF RC filter is common to both. The CS5374 modulators require a 2.500 V precision voltage reference to be supplied to the VREF pins. 7.1 VREF Power Supply To guarantee proper regulation headroom for the voltage reference device, the voltage reference GND pin should be connected to VA- instead of system ground, as shown in Figure 18. This connection results in a VREF- voltage equal to VA- and a VREF+ voltage very near ground potential [(VA-) + 2.500 VREF]. Power supply inputs to the voltage reference device should be bypassed to system ground with 0.1 F capacitors placed as close as possible to the power and ground pins. In addition to 0.1 F local bypass capacitors, at least 100 F of bulk capacitance to system ground should be placed on each power supply near the voltage regulator outputs. Bypass capacitors should be X7R, C0G, tantalum, or other high-quality dielectric type. 7.3 VREF PCB Routing To minimize the possibility of outside noise coupling into the CS5374 voltage reference input, the VREF traces should be routed as a differential pair from the large capacitor of the voltage reference RC filter. Careful control of the voltage reference source and return currents by routing VREF as a differential pair will significantly improve immunity from external noise. To further improve noise rejection of the VREF differential route, include 0.1 F bypass capacitors to system ground as close as possible to the VREF+ and VREF- pins of the CS5374. 7.2 VREF RC Filter A primary concern in selecting a precision voltage reference device is noise performance in the measurement bandwidth. The Linear Technology LT1019AIS8-2.5 voltage reference yields acceptable noise levels if the output is filtered with a lowpass RC filter. 30 7.4 VREF Input Impedance The switched-capacitor input architecture of the VREF inputs results in an input impedance that depends on the internal capacitor size and the MCLK frequency. With a 15 pF internal capacitor and a 2.048 MHz MCLK, the VREF input impedance is approximately DS862F1 CS5374 DS862F1 1 / [(2.048 MHz) x (15 pF)] = 32 k. While the size of the internal capacitor is fixed, the voltage reference input impedance can vary with MCLK. The voltage reference external RC filter series resistor creates a voltage divider with the VREF input impedance to reduce the effective applied input voltage. To minimize gain error resulting from this voltage divider effect, the RC filter series resistor should be the minimum size recommended in the voltage reference device data sheet. CS5374 7.5 VREF Accuracy The nominal voltage reference input is specified as 2.500 V across the VREF pins, and all CS5374 gain accuracy specifications are measured using a nominal voltage reference input. Any variation from a nominal VREF input will proportionally vary the analog full-scale gain accuracy. Since temperature drift of the voltage reference results in gain drift of the analog full-scale amplitude, care should be taken to minimize temperature drift effects through careful selection of passive components and the voltage reference device itself. Gain drift specifications of the CS5374 do not include the temperature drift effects of external passive components or of the voltage reference device itself. DS862F1 31 CS5374 DS862F1 0.1 uF CS5374 To VA+ Regulator 100 uF 0.1 uF VA+ VA+ VD+ 0.01 uF 100 uF To VD Regulator CS5374 VATo VARegulator 100 uF 0.1 uF VAGND 0.1 uF Figure 19. Power Supply Diagram 8. POWER SUPPLIES The CS5374 has two positive analog power supply pins (VA+), two negative analog power supply pins (VA-), a digital power supply pin (VD+), and a ground pin (GND). For proper operation, power must be supplied to all power supply pins, and the ground pin must be connected to system ground. The CS5374 digital power supply (VD+) and the CS5376A digital power supply (VD) must share a common voltage. Care should be taken to connect the CS5374 thermal pad on the bottom of the package to VA-, not system ground (GND), since it internally connects to VA- and is expected to be the most negative applied voltage. 8.2 Digital Power Supply The digital power supply across the VD and GND pins is specified for a +3.3 V power supply. The digital power supply should be bypassed to system ground using a 0.01 F X7R type capacitor. The digital power supply across the VD+ and GND pins is specified to be +3.3 V. 8.1 Analog Power Supplies The analog power pins of the CS5374 are to be supplied with a total of 5 V between VA+ and VA- from a bipolar 2.5 V supply. When using bipolar supplies the analog signal common mode voltage should be biased to 0 V. The analog power supplies are recommended to be bypassed to system ground using 0.1 F X7R type capacitors. The VA- supply is connected to the CMOS substrate and as such must remain the most negative applied voltage to prevent potential latch-up conditions. It is recommended to clamp the VA- supply to system ground using a reverse biased Schottky diode to prevent possible latch-up conditions related to mismatched supply rail initialization. 8.3 Power Supply Bypassing The VA+ and VA- power supplies should be bypassed to system ground with 0.1 F capacitors placed as close as possible to the power pins of the device. The VD+ power supply should be bypassed to system ground with 0.1 F capacitors placed as close as possible to the power pins of the device. Bypass capacitors should be X7R, C0G, tantalum, or other high-quality dielectric type. In addition to the local bypass capacitors, at least 100 F bulk capacitance to system ground should be placed on each power supply near the voltage DS862F1 32 CS5374 DS862F1 regulator output, with additional power supply bulk capacitance placed among the analog component route if space permits. CS5374 8.6 SCR Latch-up Considerations It is recommended to connect the VA- power supply to system ground (GND) through a reverse-biased Schottky diode. At power up, if the VA+ power supply ramps up before the VA- supply is established, the VA- pin voltage could be pulled above ground potential through the CS5374 device. If the VA- supply is pulled 0.7 V or more above GND, SCR latch-up can occur. A reverse-biased Schottky diode will clamp the VA- voltage a maximum of 0.3 V above ground to ensure SCR latch-up does not occur at power up. For similar reasons, care should be taken to connect the CS5374 thermal pad on the bottom of the package to VA-, not system ground (GND), since it internally connects to VA- and is expected to be the most negative applied voltage. 8.4 PCB Layers and Routing The CS5374 is a high-performance device, and special care must be taken to ensure power and ground routing is correct. Power can be supplied either through dedicated power planes or routed traces. When routing power traces, it is recommended to use a "star" routing scheme with the star point either at the voltage regulator output or at a local power supply bulk capacitor. It is also recommended to dedicate a full PCB layer to a solid ground plane, without splits or routing. All bypass capacitors should connect between the power supply circuit and the solid ground plane as near as possible to the device power supply pins. The CS5374 analog signals are differentially routed and do not normally require connection to a separate analog ground. However, if a separate analog ground is required, it should be routed using a "star" routing scheme on a separate layer from the solid ground plane and connected to the ground plane only at a single point. Be sure all active devices and passive components connected to the separate analog ground are included in the "star" route to ensure sensitive analog currents do not return through the ground plane. 8.7 DC-DC Converters Many low-frequency measurement systems are battery powered and utilize DC-DC converters to efficiently generate power supply voltages. To minimize interference effects, operate the DC-DC converter at a frequency which is rejected by the digital filter, or operate it synchronous to the MCLK rate. A synchronous DC-DC converter whose operating frequency is derived from MCLK will theoretically minimize the potential for "beat frequencies" to appear in the measurement bandwidth. However this requires the source clock to remain jitter free within the DC-DC converter circuitry. If clock jitter can occur within the DC-DC converter (as in a PLLbased architecture), it's better to use a non-synchronous DC-DC converter whose switching frequency is rejected by the digital filter. During PCB layout, do not place high-current DCDC converters near sensitive analog components. Carefully routing a separate DC-DC "star" ground will help isolate noisy switching currents away from the sensitive analog components. 33 8.5 Power Supply Rejection Power supply rejection of the CS5374 is frequency dependent. The CS5376A digital filter fully rejects power supply noise for frequencies above the selected digital filter corner frequency. Power supply noise frequencies between DC and the digital filter corner frequency are rejected as specified in the "Power Supply Characteristics" on page 13. DS862F1 CS5374 DS862F1 9. SPITM REGISTER SUMMARY CS5374 The CS5374 Configuration Registers contain the hardware configuration settings. Name VERSION AMP1CFG AMP2CFG ADCCFG PWRCFG Addr. Type # Bits Description Device Version ID Amplifier 1 configuration Amplifier 2 configuration Modulator 1 & 2 configuration Power configuration 0x00 0x01 0x02 0x03 0x04 R R/W R/W R/W R/W 8 8 8 8 8 34 DS862F1 CS5374 DS862F1 9.1 VERSION: 0x00 Figure 20. Hardware Version ID Register VERSION (MSB)7 VER7 R 0 6 VER6 R 0 5 VER5 R 0 4 VER4 R 0 3 VER3 R 0 2 VER2 R 0 1 VER1 R 0 (LSB)0 VER0 R 1 CS5374 Address: 0x00 Reset Condition : 0000_0001 (0x01) : Default value Normal Operation : 0000_0001 (0x01) : Default value Power Down Operation : 0000_0001 (0x01) : Default value Not defined (read as 0) R Readable W Writable R/W Readable and Writable Bits in bottom rows are reset condition -- Bit definitions: 7:0 VERS Hardware revision ID register 0x01: Revision A DS862F1 35 CS5374 DS862F1 9.2 AMP1CFG: 0x01 Figure 21. Amplifier 1 Configuration Register AMP1CFG (MSB)7 PWDN1 R/W 0 6 HP1 R/W 0 5 MUX1_1 R/W 0 4 MUX1_0 R/W 0 3 GUARD R/W 0 2 GAIN1_2 R/W 0 1 GAIN1_1 R/W 0 (LSB)0 GAIN1_0 R/W 0 CS5374 Address: 0x01 -- Reset Condition : 0000_0000 (0x00) : Default value Normal Operation : 00MM_GGGG : MUX, GUARD and GAIN select Power Down Operation : 1000_0000 (0x80) : PWDN enabled Not defined (read as 0) R Readable W Writable R/W Readable and Writable Bits in bottom rows are reset condition Bit definitions: 7 PWDN1 Amplifier 1 Power Down 1: enable 0: disable Amplifier 1 High Precision 1: enable 0: disable 6 HP1 5:4 MUX1[1:0] Input Multiplexer 11: INA1 + INB1 10: INA1 only 01: INB1 only 00: 800 ohm termination GUARD GUARD Output 1: disable 0: enable 3 2:0 GAIN1[2:0] Amplifier 1 Gain 111: reserved 110: 64x 101: 32x 100: 16x 011: 8x 010: 4x 001: 2x 000: 1x 36 DS862F1 CS5374 DS862F1 9.3 AMP2CFG: 0x02 Figure 22. Amplifier 2 Configuration Register AMP2CFG (MSB)7 PWDN2 R/W 0 6 HP2 R/W 0 5 MUX2_1 R/W 0 4 MUX2_0 R/W 0 3 --R/W 0 2 GAIN2_2 R/W 0 1 GAIN2_1 R/W 0 (LSB)0 GAIN2_0 R/W 0 CS5374 Address: 0x02 -- Reset Condition : 0000_0000 (0x00) : Default value Normal Operation : 00MM_0GGG : MUX and GAIN select Power Down Operation : 1000_0000 (0x80) : PWDN enabled Not defined (read as 0) R Readable W Writable R/W Readable and Writable Bits in bottom rows are reset condition Bit definitions: 7 PWDN2 Amplifier 2 Power Down 1: enable 0: disable Amplifier 2 High Precision 1: enable 0: disable 6 HP2 5:4 MUX2[1:0] Input Multiplexer 11: INA2 + INB2 10: INA2 only 01: INB2 only 00: 800 ohm termination --Reserved 3 2:0 GAIN2[2:0] Amplifier 2 Gain 111: reserved 110: 64x 101: 32x 100: 16x 011: 8x 010: 4x 001: 2x 000: 1x DS862F1 37 CS5374 DS862F1 9.4 ADCCFG: 0x03 Figure 23. Modulator 1 & 2 Configuration Register ADCCFG (MSB)7 OFST R/W 0 6 HP R/W 0 5 PWDN2 R/W 0 4 PWDN1 R/W 0 3 --R/W 0 2 --R/W 0 1 --R/W 0 (LSB)0 --R/W 0 CS5374 Address: 0x03 -- Reset Condition : 0000_0000 (0x00) : Default value Normal Operation : 0100_0000 (0x40) : HP mode enabled Power Down Operation : 0011_0000 (0x30) : PWDN enabled Not defined (read as 0) R Readable W Writable R/W Readable and Writable Bits in bottom rows are reset condition Bit definitions: 7 OFST Modulator Offset (add -60mV to Channel 1, add -35mV to Channel 2) 1: disable 0: enable Modulator High Precision 1: enable 0: disable Modulator 2 Power Down 1: enable 0: disable Modulator 1 Power Down 1: enable 0: disable Reserved 6 HP 5 PWDN2 4 PWDN1 3:0 --- 9.5 PWRCFG: 0x04 38 DS862F1 CS5374 DS862F1 Figure 24. Power Configuration Register PWRCFG (MSB)7 adc_lpwr R/W 0 6 --R/W 0 5 amp_i1_1 R/W 0 4 amp_i1_0 R/W 0 3 rough R/W 0 2 i1_tail R/W 0 1 amp_i5_1 R/W 0 (LSB)0 amp_i5_0 R/W 0 CS5374 Address: 0x04 Reset Condition : 0000_0000 (0x00) : Default value Normal Operation : 1000_1111 (0x8F) : Reduced power Power Down Operation : 0000_0000 (0x00) : Default value Not defined (read as 0) R Readable W Writable R/W Readable and Writable Bits in bottom rows are reset condition. --- Bit definitions: 7 adc_lpwr Modulator Bias 1: reduced current 0: nominal current reserved Amplifier i1 Bias 11: 2/3 10: 1/3 01: 4/3 00: nominal current Modulator Rough Phase 1: reduced current 0: nominal current Amplifier i1 Tail Current 1: reduced current 0: nominal current Amplifier i5 Bias 11: 7/11 10: 9/13 01: 15/13 00: nominal current 6 5:4 --amp_i1 3 rough 2 i1_tail 1:0 amp_i5 DS862F1 39 CS5374 DS862F1 10. PIN DESCRIPTIONS GUARD1 OUT1+ OUT1INR1INF1INF1+ INR1+ NC VAVA+ NC RST CS5374 Pin 1 Location Indicators 48 47 46 45 44 43 42 41 40 39 38 INA1+ INA1INB1INB1+ DNC VA+ VADNC INB2+ INB2INA2INA2+ 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 THERMAL PAD CONNECT TO VA- 32 31 30 29 28 27 26 25 MCLK MSYNC MDATA1 MFLAG1 VD+ GND MDATA2 MFLAG2 SDO SDI SCLK CS Pin Name Pin Number VA+ VA- VD+, GND INA1+ INA1- INB1-, INB1+ INB2+, INB2- INA2-, INA2+ 40 6, 39 7, 40 32, 31 1 2 3 4 9 10 11 12 Differential Amplifier Analog Inputs GUARD2 OUT2+ OUT2INR2INF2INF2+ INR2+ NC VREF+ VREFNC NC Top-Down (Though Package) View Pin Type Power Supplies Pin Description Analog power supply. Refer to the Specified Operating Conditions. Digital power supply. Refer to the Specified Operating Conditions. I I I I I I Channel 1 differential analog input A. Selected via Serial Communications Interface. Channel 1 differential analog input B. Selected via Serial Communications Interface. Channel 2 differential analog input B. Selected via Serial Communications Interface. Channel 2 differential analog input A. Selected via Serial Communications Interface. DS862F1 CS5374 DS862F1 Differential Amplifier Analog Outputs CS5374 OUT1-, OUT1+ GUARD1 GUARD2 OUT2+, OUT2- INR1+, INF1+, INF1-, INR1- INR2-, INF2-, INF2+, INR2+ VREF+, VREF- CS SCLK SDI SDO MCLK MSYNC MFLAG1 MDATA1 MFLAG2 MDATA2 RST NC DNC Thermal Pad 46 47 48 13 14 15 42 43 44 45 16 17 18 19 21 22 25 26 27 28 36 35 33 34 29 30 37 20, 23, 24, 38, 41 5, 8 49 O O O O Channel 1 differential analog output. Guard output voltage for analog input Channel 1. Guard output voltage for analog input Channel 2. Channel 2 differential analog output. Modulator Analog Inputs I Channel 1 analog differential rough and fine inputs. From the Channel 1 differential anti-alias filter. I Channel 2 analog differential rough and fine inputs. From the Channel 2 differential anti-alias filter. Voltage Reference I Voltage reference input. Refer to the Specified Operating Conditions. Serial Interface I I I O I I O O O O I ----I Chip select. Active low. Serial clock. Serial data in to device. Serial data out of device. Modulator Interface Modulator clock input. Modulator sync input. Channel 1 modulator flag output. Channel 1 modulator data output. Channel 2 modulator flag output. Channel 2 modulator data output. Device Reset Reset. Active low. Other No connect. Do Not Connect. Connect to VA-. Do not connect to GND. DS862F1 41 CS5374 DS862F1 11. PACKAGE DIMENSIONS 48-PIN QFN (7MM X 7MM) CS5374 42 DS862F1 CS5374 DS862F1 12. ORDERING INFORMATION Model Number Temperature Package CS5374 CS5374-CNZ, lead (Pb) free -10 to +70 C 48-Pin QFN 13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5374-CNZ, lead (Pb) free 260 C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS862F1 43 CS5374 DS862F1 14. REVISION HISTORY Revision Date Changes CS5374 T1 A1 A2 PP1 F1 AUG 2008 DEC 2008 JAN 2009 APR 2009 OCT 2009 Initial release of Target data sheet. Initial release of Advanced data sheet. Update to include more complete characterization data. Specify operation for 2.048 MHz MCLK and HP mode. Add PWRCFG register. Update to include more complete characterization data. Update to include final characterization data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY, SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. 44 DS862F1 |
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